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april 1999 1 ? 1999 actel corporation advanced v.1 54sxa family fpgas specifications ? 8,000 to 72,000 available logic gates ? up to 360 user-programmable i/o pins ? 4,024 flip-flops ? 0.25 micro cmos features ? i/os with live, or hot, insertion/removal capability ? power up/down friendly (no sequencing required for supply voltage) ? 66 mhz pci ? cpld and fpga integration ? single chip solution ? configurable i/os to support varity of i/o standards, such as 3.3v pci, lvttl, ttl, and 5v pci. ? configurable weak resistor pullup or pulldown for output tristate at powerup ? 100% resource utilization with 100% pin locking ? 2.5v, 3.3v, and 5.0v mixed voltage operation with 5.0v input tolerance ? very low power consumption ? deterministic, user-controllable timing ? unique in-system diagnostic and debug capability with silicon explorer ? jtag boundary scan testing in compliance with ieee standard 1149.1 ? actel designer series design tools, supported by cadence, exemplar, ist, mentor graphics, model tech, synopsys, synplicity, and viewlogic design entry and simulation tools ? secure programming technology prevents reverse engineering and design theft sx product profile a54sx08a a54sx16a a54sx32a a54sx72a gate capacity 8,000 16,000 32,000 72,000 logic modules 768 1,452 2,880 6,036 combinatorial cells 512 924 1,800 4,024 register cells (dedicated flip-flops) 256 528 1,080 2,012 maximum flip-flops 512 990 1,980 4,024 user i/os (maximum) 130 177 249 360 clocks 3333 quadrant clocks 0004 jtag ye s ye s ye s ye s pci ye s ye s ye s ye s clock-to-out tbd tbd 4.5 ns 4.8 ns input set-up (external) tbd tbd -1.3 ns -3.3 ns speed grades std, C1, C2, C3 std, C1, C2, C3 std, C1, C2, C3 std, C1, C2, C3 temperature grades c, i, m c, i, m c, i, m c, i, m packages (by pin count) pqfp tqfp pbga 208 100, 144 144 208 100, 144 144 208 144 144, 256, 329 208 484
2 general description the new sxa family of fpgas actels sxa family of fpgas features a revolutionary new sea-of-modules architecture that delivers next-generation device performance and integration levels not currently achieved by any other fpga architecture. sxa devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further speed time-to-market for performance-intensive applications. fast and flexible new architecture actels sxa architecture features two types of logic modules, the combinatorial cell (c-cell) and the register cell (r-cell), each optimized for fast and efficient mapping of synthesized logic functions. optimal use of the silicon is made by locating the routing and interconnect resources in the metal layers above the logic modules. this enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or sea-of-modules), which reduces the distance signals have to travel between logic modules. to minimize signal propagation delay, sxa devices employ both local and general routing resources. the high-speed local routing resources (directconnect and fastconnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. the general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or i/o module. within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (typically 90% of connections use only three antifuses). the unique local and general routing structure featured in sxa devices gives fast and predictable performance, allows 100% pin-locking with full logic utilization, enables concurrent pcb development, reduces design time, and allows designers to achieve performance goals with a minimum of effort. further complementing the sxas flexible routing structure is a hard-wired, constantly-loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the i/o cells to achieve fast clock-to-out or fast input set-up times. sxa devices have easy-to-use i/o cells which do not require hdl instantiation, facilitating design re-use and reducing design and debugging time. ordering information application (temperature range) blank = commercial (0 to +70 c) i = industrial (C40 to +85 c) m = military (C55 to +125 c) pp = pre-production package type bg = 1.27mm ball grid array fbg = 1.0 mm ball grid array pq = plastic quad flat pack tq = thin (1.4 mm) quad flat pack speed grade blank = standard speed C1 = approximately 15% faster than standard C2 = approximately 25% faster than standard C3 = approximately 35% faster than standard part number a54sx08a = 8,000 gates a54sx16a = 16,000 gates a54sx32a = 32,000 gates a54sx72a = 72 , 000 gates package lead count a54sx16 C pq 208 2 a = 0.25 micro cmos technology a
3 54sxa family fpgas product plan speed grade* application std C1 C2 C3 c i ? m ? a54sx08a device 100-pin thin quad flat pack (tqfp) pppp ppp 144-pin thin quad flat pack (tqfp) pppp ppp 208-pin plastic quad flat pack (pqfp) pppp ppp 144-pin plastic ball grid array (fbga) pppp ppp a54sx16a device 100-pin thin quad flat pack (tqfp) pppp ppp 144-pin thin quad flat pack (tqfp) pppp ppp 208-pin plastic quad flat pack (pqfp) pppp ppp 144-pin plastic ball grid array (fbga) pppp ppp 256-pin plastic ball grid array (fbga) pppp ppp a54sx32a device 144-pin thin quad flat pack (tqfp) pppp ppp 208-pin plastic quad flat pack (pqfp) 144-pin plastic ball grid array (fbga) 4 p 4 p 4 p p p 4 p 4 p p p 256-pin plastic ball grid array (fbga) 329-pin plastic ball grid array (bga) p 4 p 4 p 4 p p p 4 p 4 p p a54sx72a device 208-pin plastic quad flat pack (pqfp) 444 p 44 p 484-pin plastic ball grid array (fbga) 444 p 44 p consult your local actel sales representative for product availability. applications: c = commercial availability: 4 = available *speed grade: C1 = approx. 15% faster than standard i = industrial p = planned C2 = approx. 25% faster than standard m = military = not planned C3 = approx. 35% faster than standard ? only std, C1, C2 speed grade ? only std, C1 speed grade plastic device resources user i/os (including clock buffers) device pqfp 208-pin tqfp 100-pin tqfp 144-pin fbga 144-pin fbga 256-pin bga 329-pin fbga 484-pin a54sx08a 130 81 113 tbd a54sx16a 175 81 113 tbd a54sx32a 174 113 tbd tbd 249 a54sx72a 173 360 package definitions (consult your local actel sales representative for product availability.) pqfp = plastic quad flat pack, tqfp = thin quad flat pack, bga = 1.27mm plastic ball grid array, fbga = 1.0mm plastic ball grid array.
4 pin description clka/b clock a and b ttl/3.3v pci clock input for clock distribution networks. the clock input is buffered prior to clocking the r-cells. if not used, this pin must be set low or high on the board. it must not be left floating. qclka/b/c/d quadrant clock a, b, c, and d these four pins are the quadrant clock inputs. they are ttl/3.3v pci clock input for clock distribution networks. each of these clock inputs can drive up to a quarter of the chip, and they can be grouped together to drive multiple quadrants. the clock input is buffered prior to clocking the r-cells. if not used, this pin must be set low or high on the board. it must not be left floating. (these quadrant clocks are only for 54sx72a). tck test clock test clock input for diagnostic probe and device programming. in flexible mode (refer to the jtag pins functionality table), tck becomes active when the tms pin is set low. this pin functions as an i/o when the jtag state machine reaches the logic reset state. gnd ground low supply voltage. hclk dedicated (hard-wired) array clock ttl clock input for sequential modules. this input is directly wired to each r-cell and offers clock speeds independent of the number of r-cells being driven. if not used, this pin must be set low or high on the board. it must not be left floating. i/o input/output the i/o pin functions as an input, output, three-state, or bi-directional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are tri-stated by the designer series software. tms test mode select the tms pin controls the use of jtag pins (tck, tdi, tdo). in flexible mode (refer to the jtag pins functionality table), when the tms pin is set low, the tck, tdi, and tdo pins are jtag pins. once the jtag pins are in jtag mode they will remain in jtag mode until the internal jtag state machine reaches the logic reset state. at this point the jtag pins will be released and will function as regular i/o pins. the logic reset state is reached 5 tck cycles after the tms pin is set high. in dedicated jtag mode, tms functions as specified in the ieee 499.1 jtag specifications. jtag operation is further described on page 10. nc no connection this pin is not connected to circuitry within the device. pra probe a the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. prb probe b the probe b pin is used to output data from any node within the device. this diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. tdi test data input serial input for jtag and diagnostic probe. in flexible mode, (refer to the jtag pins functionality table), tdi is active when the tms pin is set low. this pin functions as an i/o when the jtag state machine reaches the logic reset state. tdo test data output serial output for jtag. in flexible mode (refer to the jtag pins functionality table), tdo is active when the tms pin is set low. this pin functions as an i/o when the jtag state machine reaches the logic reset state. v cci supply voltage supply voltage for i/os. v cca supply voltage supply voltage for array. table 1 ? supply voltages v cca v cci maximum input tolerance maximum output drive a54sx08a a54sx16a a54sx32a a54sx72a 2.5v 2.5v 5.0v 2.5v 2.5v 3.3v 5.0v 3.3v 2.5v 5.0v 5.0v 5.0v
5 54sxa family fpgas sxa family architecture the sxa family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. programmable interconnect element actels new sxa family provides much more efficient use of silicon by locating the routing interconnect resources between the metal 2 (m2) and metal 3 (m3) layers (see figure 1). this completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on sram fpgas and previous generations of antifuse fpgas), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. interconnection between these logic modules is achieved using actels patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the m2 and m3 layers. the antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. the extremely small size of these interconnect elements gives the sxa family abundant routing resources and provides excellent protection against design pirating. reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. figure 1 ? sxa family interconnect elements silicon substrate tungsten plug contact metal 1 metal 2 metal 3 routing tracks amorphous silicon/ dielectric antifuse tungsten plug via tungsten plug via
6 logic module design the sxa family architecture has been called a sea-of-modules architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing (see figure 2). actel provides two types of logic modules, the r-cell and the c-cell. the r-cell (or register cell) contains a flip-flop featuring more control signals than in previous actel architectures, including asynchronous clear, asynchronous preset, and clock enable (using the s0 and s1 lines). the r-cell (figure 3) registers feature programmable clock polarity, selectable on a register-by-register basis. this provides the designer with additional flexibility while allowing mapping of synthesized functions into the sxa fpga. the clock source for the r-cell can be chosen from the hard-wired clock or the routed clock. the c-cell (or combinatorial cell, figure 4) implements a range of combinatorial functions up to 5-inputs. inclusion of the db input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the sxa architecture. an example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-or function into a single c-cell. this facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. at the same time, the c-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. chip architecture the sxa familys chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. figure 2 ? channelled array and sea-of-modules architectures channelled array architecture sea-of-modules architecture
7 54sxa family fpgas module organization actel has arranged all c-cell and r-cell logic modules into horizontal banks called clusters . there are two types of clusters: type 1 contains two c-cells and one r-cell, while type 2 contains one c-cell and two r-cells. to increase design efficiency and device performance, actel has further organized these modules into superclusters (see figure 5). supercluster 1 is a two-wide grouping of type 1 clusters. supercluster 2 is a two-wide group containing one type 1 cluster and one type 2 cluster. sxa devices feature significantly more supercluster 1 modules than supercluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. routing resources clusters and superclusters can be connected through the use of two innovative new local routing resources called fastconnect and directconnect which enable extremely fast and predictable interconnection of modules within clusters and superclusters (see figure 6 and figure 7). this routing architecture also dramatically reduces the figure 3 ? r-cell figure 4 ? c-cell direct connect input clka, clkb, internal logic hclk cks ckp clrb psetb y dq routed data input s0 s1 d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y
8 figure 5 ? cluster organization figure 6 ? directconnect and fastconnect for type 1 superclusters type 1 supercluster type 2 supercluster cluster 1 cluster 2 cluster 2 cluster 1 r-cell c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y direct connect input clka, clkb, internal logic hclk cks ckp clrb psetb y dq routed data input s0 s1 type 1 superclusters routing segments ?typically 2 antifuses ?max. 5 antifuses fast connect ?one antifuse ?0.4 ns routing delay direct connect ?no antifuses ?0.1 ns routing delay
9 54sxa family fpgas number of antifuses required to complete a circuit, ensuring the highest possible performance. directconnect is a horizontal routing resource that provides connections from a c-cell to its neighboring r-cell in a given supercluster. directconnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. fastconnect enables horizontal routing between any two logic modules within a given supercluster, and vertical routing with the supercluster immediately below it. only one programmable connection is used in a fastconnect path, delivering maximum pin-to-pin propagation of 0.2 ns. in addition to directconnect and fastconnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. actels segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place and route software to minimize signal propagation delays. actels high-drive routing structure provides three clock networks. the first clock, called hclk, is hard-wired from the hclk buffer to the clock select mux in each r-cell. this provides a fast propagation path for the clock signal, enabling the 4.0 ns clock-to-out (pin-to-pin) performance of the sxa devices. the hard-wired clock is tuned to provide clock skew as low as 0.25 ns. the remaining two clocks (clka, clkb) are global clocks that can be sourced from external pins or from internal signal logic within the sxa device. other architecture features technology actels sxa family of fpgas is implemented in high-voltage twin-well cmos using three layers of metal and 0.25 micron design rules (moving quickly to 0.22 micron). the m2/m3 antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals, and has a programmed (on state) resistance of 25 ohms with capacitance of 1.6 ff for low signal impedance. performance the combination of architectural features described above enables sxa devices to operate with internal clock frequencies exceeding 300 mhz, enabling very fast execution of even complex logic functions. thus, the actel sxa family is an optimal platform upon which to integrate the functionality previously contained in multiple figure 7 ? directconnect and fastconnect for type 2 superclusters type 2 superclusters routing segments ?typically 2 antifuses ?max. 5 antifuses fast connect ?one antifuse ?0.4 ns routing delay direct connect ?no antifuses ?0.1 ns routing delay
10 cplds. in addition, designs which previously would have required a gate array to meet performance goals can now be integrated into an sxa device with dramatic improvements in cost and time-to-market. using timing-driven place and route tools, designers can achieve highly deterministic device performance. with sxa devices, designers can achieve a higher level of performance without recourse to complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macros in hdl code. i/o modules each i/o on an sxa device can be configured as an input, an output, a tri-state output, or a bi-directional pin. even without the inclusion of dedicated i/o registers, these i/os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 4.0 ns, and external set-up time as low as 0.6 ns. i/o cells including embedded latches and flip-flops require instantiation in hdl code, a complication not required by sxa fpgas. fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reducing overall design time. power requirements the sxa family supports 3.3-volt operation and is designed to tolerate 5-volt inputs. power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. power requirements are further reduced due to the small number of antifuses in the path, and because of the low resistance properties of the antifuses. the antifuse architecture does not require active circuitry to hold a charge (as an sram or eprom does), thereby making it the lowest-power architecture on the market. jtag all sxa devices are ieee 1149.1 (jtag) compliant. sxa devices offer superior diagnostic and testing capabilities by providing jtag and probing capabilities. these functions are controlled through the special jtag pins in conjunction with the program fuse. the functionality of each pin is described in table 2. in the dedicated jtag mode, tck, tdi and tdo are dedicated jtag pins and cannot be used as regular i/os. in flexible mode, tms should be set high through a pull-up resistor of 10k ohm. tms can be pulled low to initiate the jtag sequence. table 2 ? jtag program fuse blown (dedicated jtag mode) program fuse not blown (flexible mode) tck, tdi, tdo are dedi- cated jtag pins tck, tdi, tdo are ?exible and may be used as i/os no need for pull-up resistor for tms use a pull-up resistor of 10k ohm on tms
11 54sxa family fpgas the program fuse determines whether the device is in dedicated or flexible mode. the default (fuse not blown) is flexible mode. design tool support as with all actel fpgas, the new sxa family is fully supported by actels designer series development tools, which include: ? directtime for automated, timing-driven place and route; ? actgen for fast development using a wide range of macro functions; and ? actmap for logic synthesis. designer series supports industry-leading vhdl and verilog-based design tools, including synthesis tools from industry leaders such as exemplar logic, synplicity, and synopsys. silicon explorer and sxa fpga actel sxa fpgas include internal probe circuitry to dynamically observe and analyze any signal inside the fpga during normal device operation. the probe circuitry is accessed and controlled by silicon explorer--an integrated debugging and logic analysis tool that attaches to a pc. silicon explorer is also an 18-channel logic analyzer that samples data at 100 mhz (asynchronous) or 66 mhz (synchronous). two channels of the logic analyzer have a direct connection to pra and prb pins, which can automatically display any two signals inside the fpga. the remaining 16 channels of the logic analyzer can be used to examine other signals on the board. in addition, silicon explorer can read back the designs checksum, allowing designers to verify that the correct design was programmed in the fpga. sxa probe circuit control pins the silicon explorer tool uses the jtag ports (tdi, tck, tms and tdo) to select the desired nets for debugging. the selected internal nets are assigned to the pra/prb pins for observation. figure 8 illustrates the interconnection between silicon explorer and the fpga to perform in-circuit debugging. design considerations avoid using the tdi, tck, tdo, pra and prb pins as input or bi-directional ports. because these pins are active during probing, critical signal input through these pins is not available while probing. in addition, do not program the security fuse. programming the security fuse disables the probe circuitry. figure 8 ? probe setup sx fpga silicon explorer tdi tck tdo tms pra prb serial connection 18 channel
12 3.3v/5v operating conditions absolute maximum ratings 1 symbol parameter limits units v cci dc supply voltage 2 C0.3 to +6.0 v v cca dc supply voltage C0.3 to +2.7 v v i input voltage C0.5 to +5.5 v v o output voltage C0.5 to +3.6 v i io i/o source sink current 3 C30 to +5.0 ma t stg storage temperature C40 to +125 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd C 0.5v, the internal protection diodes will forward-bias and can draw excessive current. recommended operating conditions parameter commercial industrial military units temperature range 1 0 to +70 C40 to +85 C55 to +125 c 3.3v power supply tolerance 10 10 10 %v cc 5v power supply tolerance 5 10 10 %v cc note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military.
13 54sxa family fpgas electrical specifications pci compliance for the 54sxa family the 54sxa family supports 3.3v and 5v pci and is compliant with the pci local bus specification rev. 2.1. dc specifications (5.0v pci operation) commercial industrial symbol parameter min. max. min. max. units v oh (i oh = -20ua) (cmos) (i oh = -8ma) (ttl) (i oh = -6ma) (ttl) (v cci C 0.1) 2.4 v cci v cci (v cci C 0.1) 2.4 v cci v cci v v ol (i ol = 20ua) (cmos) (i ol = 12ma) (ttl) (i ol = 8ma) (ttl) 0.10 0.50 0.50 v v il 0.8 0.8 v v ih 2.0 2.0 v t r , t f input transition time t r , t f 50 50 ns c io c io i/o capacitance 10 10 pf i cc standby current, i cc 4.0 4.0 ma i cc(d) i cc(d) i dynamic v cc supply current see evaluating power in 54sxa devices on page 20. table 3 ? dc specifications for 5v signaling symbol parameter condition min. max. units v cca supply voltage for array 2.3 2.7 v v cci supply voltage for ios 4.75 5.25 v v ih input high voltage 1 2.0 v cc + 0.5 v v il input low voltage 1 C0.5 0.8 v i ih input high leakage current v in = 2.7 70 a i il input low leakage current v in = 0.5 C70 a v oh output high voltage i out = C2 ma 2.4 v v ol output low voltage 2 i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 4 8pf notes: 1. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 2. signals without pull-up resistors must have 3 ma low output current. signals requiring pull up must have 6 ma; the latter include, frame#, irdy#, irdy#, devsel#, stop#, serr#, perr#, lock#, and, when used ad[63::32], c/be[7::4]#, par64, req64#, and ack64#. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk) with an exception granted to motherboard-only devices, which could be up to 16 pf, in order to accommodate pga packaging. this would mean, in general, that components for expansion boards would need to use alternatives to ceramic pga packaging (i.e., pqfp, sga, etc.). 4. lower capacitance on this input-only pin allows for non-resistive coupling to ad[xx].
14 ac specifications (5.0v pci operation) table 4 ? ac specifications for 5v signaling symbol parameter condition min. max. units i oh(ac) switching 1 current high 1, 2 1, 3 (test point) 3 0 < v out 1.4 1.4 v out < 2.4 3.1 < v out < v cc v out = 3.1 C44 C44 + (v out C 1.4)/0.024 eq. a C142 ma ma ma i ol(ac) switching 1 current high 1 1, 3 (test point) 3 v out 3 2.2 2.2 > v out > 0.55 0.71 > v out > 0 v out = 0.71 95 v out /0.023 eq. b 206 ma ma ma i cl low clamp current C5 < v in C1 C25 + (v in + 1)/0.015 ma slew r output rise slew rate 4 0.4v to 2.4v load 1 5 v/ns slew f output fall slew rate 4 2.4v to 0.4v load 1 5 v/ns notes: 1. refer to the v/i curves in figure 9. switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst# which are system outputs. switching current high specification are not relevant to serr#, inta#, intb#, intc#, and intd# which are open drain outputs. 2. note that this segment of the minimum current curve is drawn from the ac drive point directly to the dc drive point rather than toward the voltage rail (as is done in the pull-down curve). this difference is intended to allow for an optional n-channel pull-up. 3. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (a and b) are provided with the respective diagrams in figure 9. the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the pci local bus specification. however, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity modeling accounts for this. rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. vcc 1k w 10 pf 1k w pin
15 54sxa family fpgas figure 9 shows the 5.0v pci v/i curve and the minimum and maximum pci drive characteristics of the a54sx16p family. equation a: i oh = 11.9 * (v out C 5.25) * (v out + 2.45) for v cc > v out > 3.1v equation b: i ol = 78.5 * v out * (4.4 C v out ) for 0v < v out < 0.71v figure 9 ? 5.0v pci curve for sxa family 1 23456 ?.20 ?.15 ?.10 ?.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 voltage out current (a) sx pci i ol sx pci i oh pci i ol maximum pci i oh maximum pci i oh mininum pci i ol mininum
16 dc specifications (3.3v pci operation) table 5 ? dc specifications for 3.3v signaling symbol parameter condition min. max. units v cca supply voltage for array 2.3 2.7 v v cci supply voltage for ios 3.0 3.6 v v ih input high voltage 0.5v cc v cc + 0.5 v v il input low voltage C0.5 0.3v cc v i ipu input pull-up voltage 1 0.7v cc v i il input leakage current 2 0 < v in < v cc 10 a v oh output high voltage i out = C500 a 0.9v cc v v ol output low voltage i out = 1500 a 0.1v cc v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 4 8pf notes: 1. this specification should be guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pull a floated network. applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 3. absolute maximum pin capacitance for a pci input is 10pf (except for clk) with an exception granted to motherboard-only devices, which could be up to 16 pf, in order to accommodate pga packaging. this would mean in general that components for expansion boards would need to use alternatives to ceramic pga packaging. this would mean in general that components for expansion boards would need to use alternatives to ceramic packaging; i.e., pqfp, sga, etc. 4. lower capacitance on this input-only pin allows for non-resistive coupling to ad[xx].
17 54sxa family fpgas ac specifications (3.3v pci operation) table 6 ? ac specifications for 3.3v signaling symbol parameter condition min. max. units i oh(ac) switching 1 current high 1 1, 2 (test point) 2 0 < v out 0.3v cc 0.3v cc v out < 0.9v cc 0.7v cc < v out < v cc v out = 0.7v cc C12v cc C17.1 + (v cc C v out ) eq. c C32v cc ma ma ma i ol(ac) switching 1 current high 1 1, 2 (test point) 2 v cc > v out 3 0.6v cc 0.6v cc > v out > 0.1v cc 0.18v cc > v out > 0 v out = 0.18v cc 16v cc 26.7v out eq. d 38v cc ma ma ma i cl low clamp current C3 < v in C1 C25 + (v in + 1)/0.015 ma i ch high clamp current C3 < v in C1 25 + (v in C v out C 1)/0.015 ma slew r output rise slew rate 3 0.2v cc to 0.6v cc load 1 4 v/ns slew f output fall slew rate 3 0.6v cc to 0.2v cc load 1 4 v/ns notes: 1. refer to the v/i curves in figure 10. switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst# which are system outputs. switching current high specification are not relevant to serr#, inta#, intb#, intc#, and intd# which are open drain outputs. 2. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (c and d) are provided with the respective diagrams in figure 10. the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the pci local bus specification. however, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. vcc 1k w 10 pf 1k w pin
18 figure 10 shows the 3.3v pci v/i curve and the minimum and maximum pci drive characteristics of the sxa family. equation c: i oh = (98.0/v cc ) * (v out C v cc ) * (v out + 0.4v cc ) for v cc > v out > 0.7 v cc equation d: i ol = (256/v cc ) * v out * (v cc C v out ) for 0v < v out < 0.18 v cc figure 10 ? 3.3v pci curve for sxa family 123456 voltage out ?.20 ?.15 ?.10 ?.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current (a) sx pci i ol sx pci i oh pci i ol maximum pci i oh maximum pci i oh minimum pci i ol minimum
19 54sxa family fpgas power-up sequencing power-down sequencing junction temperature (t j ) the temperature that you select in designer series software is the junction temperature, not ambient temperature. this is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. use equation 4, shown below, to calculate junction temperature. junction temperature = d t + t a (4) where: t a = ambient temperature d t = temperature gradient between junction (silicon) and ambient d t = q ja * p p = power calculated from estimating power consumption section q ja = junction to ambient of package. q ja numbers are located in package thermal characteristics section. package thermal characteristics the device junction to case thermal characteristic is q jc , and the junction to ambient air characteristic is q ja . the thermal characteristics for q ja are shown with two different air flow rates. the maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a tqfp 144-pin package at commercial temperature and still air is as follows: v cca v cci power-up sequence comments a54sx08a, a54sx16a, a54sx32a, a54sx72a 2.5v 2.5v v cca first v cci second no possible damage to device. v cci first v cca second no possible damage to device. 2.5v 3.3v 2.5v first 3.3v second no possible damage to device. 3.3v first 2.5v second no possible damage to device. 2.5v 5.0v 2.5v first 5.0v second no possible damage to device. 5.0v first 2.5v second no possible damage to device. v cca v cci power-down sequence comments a54sx08a, a54sx16a, a54sx32a, a54sx72a 2.5v 2.5v v cca first v cci second no possible damage to device. v cci first v cca second no possible damage to device. 2.5v 3.3v 2.5v first 3.3v second no possible damage to device. 3.3v first 2.5v second no possible damage to device. 2.5v 5.0v 2.5v first 5.0v second no possible damage to device. 5.0v first 2.5v second no possible damage to device.
20 temperature and voltage derating factors (normalized to worst-case commercial, t j = 70 c, v cca = 2.7v) package type pin count q jc q ja still air q ja 300 ft/min units thin quad flatpack (tqfp) 100 12 37.5 30 c/w thin quad flatpack (tqfp) 144 10 32 24 c/w plastic quad flatpack (pqfp) with heat spreader 208 8 18 14 c/w plastic ball grid array (fbga) 144 3.8 38.8 26.7 c/w plastic ball grid array (fbga) 256 3.3 30 25 c/w plastic ball grid array (bga) 329 3 18 13.5 c/w plastic ball grid array (fbga) 484 0.8 20 15 c/w maximum power allowed max. junction temp. ( c)C max. ambient temp. ( c) q ja ( c/w) ------------------------------------------------------------------------------------------------------------------------- - 150 cC 70 c 32 c/w ---------------------------- - 2.5w === v cca junction temperature (t j ) C55 C40 0 25 70 85 125 2.3 0.80 0.85 0.94 0.95 1.07 1.11 1.24 2.5 0.75 0.79 0.88 0.89 1.00 1.04 1.16 2.7 0.71 0.74 0.83 0.84 0.94 0.98 1.09
21 54sxa family fpgas 54sxa timing model* hard-wired clock external set-up = t iny + t ird1 + t sud C t hckl = 0.6 + 0.3 + 0.4 C 1.1 = 0.2 ns clock-to-out (pin-to-pin) =t hckl + t rco + t rd1 + t dhl = 1.1 + 0.8 + 0.3 + 2.3 = 4.5 ns routed clock external set-up = t iny + t ird1 + t sud C t rckh = 0.6 + 0.3 + 0.4 C 2.6 = -1.3 ns clock-to-out (pin-to-pin) =t rckh + t rco + t rd1 + t dhl = 2.6 + 0.8 + 0.3 + 2.3 = 6.0 ns timing characteristics timing characteristics for 54sxa devices fall into three categories: family-dependent, device-dependent, and design-dependent. the input and output buffer characteristics are common to all 54sxa family members. internal routing delays are device dependent. design dependency means actual delays are not determined until after placement and routing of the users design is complete. delay values may then be determined by using the directtime analyzer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most time-critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. *values shown for a54sx32a-3, worst-case commercial conditions. output delays internal delays input delays hard-wired i/o module f hmax = 320 mhz t iny = 0.6 ns t ird2 = 0.4 ns combinatorial cell t pd =0.81ns register cell i/o module t rd1 = 0.3 ns t dhl = 2.3 ns i/o module routed clock f max = 250 mhz d q d q t dhl = 2.3 ns t enzl = 1.3 ns t rd1 = 0.3 ns t rco = 0.8 ns t sud = 0.4 ns t hd = 0.0 ns t rd4 = 0.7 ns t rd8 = 1.3 ns predicted routing delays t rckh = 2.6 ns (100% load) t rd1 = 0.3 ns register cell t rco = 0.8 ns clock t hckl = 1.1 ns
22 output buffer delays ac test loads input buffer delays c-cell delays to ac test loads (shown below) pa d d e tribuff in v cc gnd 50% out v ol v oh 1.5v t dlh 50% 1.5v t dhl en v cc gnd 50% out v ol 1.5v t enzl 50% 10% t enlz en v cc gnd 50% out gnd v oh 1.5v t enzh 50% 90% t enhz v cc load 1 (used to measure load 2 (used to measure enable delays) 35 pf to the output v cc gnd 35 pf to the output r to v cc for t pzl r to gnd for t pzh r = 1 k w propagation delay) under test under test load 3 (used to measure disable delays) v cc gnd 5 pf to the output r to v cc for t plz r to gnd for t phz r = 1 k w under test pa d y inbuf in 3v 0v 1.5v out gnd v cc 50% t iny 1.5v 50% t iny s a b y s, a or b out gnd v cc 50% t pd out gnd gnd v cc 50% 50% 50% v cc 50% 50% t pd t pd t pd
23 54sxa family fpgas register cell timing characteristics flip-flops (positive edge triggered) d clk clr q d clk q clr t hpwh , t wasyn t hd t sud t hp t hpwl , t rco t clr t rpwl t rpwh preset t preset preset
24 long tracks some nets in the design use long tracks. long tracks are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes five antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 4 ns to 8.4 ns delay. this additional delay is represented statistically in higher fanout (fo=24) routing delays in the data sheet specifications section. timing derating 54sxa devices are manufactured in a cmos process. therefore, device performance varies according to temperature, voltage, and process variations. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
25 54sxa family fpgas a54sx32a timing characteristics (worst-case commercial conditions, v cca, v cci = 3.0v, t j = 70 c) c-cell propagation delays 1 C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t pd internal array module 0.8 0.9 1.1 1.3 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.1 0.2 0.2 0.2 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 ns t rd2 fo=2 routing delay 0.4 0.5 0.6 0.7 ns t rd3 fo=3 routing delay 0.6 0.7 0.8 0.9 ns t rd4 fo=4 routing delay 0.7 0.9 1.0 1.1 ns t rd8 fo=8 routing delay 1.3 1.5 1.7 2.1 ns t rd12 fo=12 routing delay 1.9 2.2 2.5 3.0 ns r-cell timing t rco sequential clock-to-q 0.8 0.9 1.0 1.2 ns t clr asynchronous clear-to-q 0.6 0.7 0.8 0.9 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 ns t sud flip-flop data input set-up 0.4 0.5 0.6 0.7 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.0 1.2 1.4 1.6 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
26 a54sx32a timing characteristics (continued) (worst-case commercial conditions) i/o module input propagation delays C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t inyh input data pad-to-y high 0.6 0.7 0.8 0.9 ns t inyl input data pad-to-y low 0.9 1.0 1.2 1.4 ns predicted input routing delays 1 t ird1 fo=1 routing delay 0.3 0.3 0.4 0.5 ns t ird2 fo=2 routing delay 0.4 0.5 0.6 0.7 ns t ird3 fo=3 routing delay 0.6 0.7 0.8 0.9 ns t ird4 fo=4 routing delay 0.7 0.9 1.0 1.1 ns t ird8 fo=8 routing delay 1.3 1.5 1.7 2.1 ns t ird12 fo=12 routing delay 1.9 2.2 2.5 3.0 ns note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
27 54sxa family fpgas a54sx32a timing charateristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) i/o module C pci output timing 1 C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.4 2.8 3.2 3.7 ns t dhl data-to-pad high to low 2.3 2.7 3.1 3.6 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 ns t enzh enable-to-pad, z to h 1.6 1.9 2.1 2.5 ns t enlz enable-to-pad, l to z 2.6 2.9 3.3 3.9 ns t enhz enable-to-pad, h to z 2.9 3.3 3.8 4.4 ns note: 1. delays based on 10pf loading. i/o module C ttl output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 3.2 3.7 4.2 4.9 ns t dhl data-to-pad high to low 2.8 3.3 3.7 4.4 ns t enzl enable-to-pad, z to l 2.6 3.0 3.4 4.0 ns t enzh enable-to-pad, z to h 3.2 3.7 4.2 4.9 ns t enlz enable-to-pad, l to z 2.1 3.2 3.6 4.2 ns t enhz enable-to-pad, h to z 3.3 3.8 4.3 5.0 ns
28 a54sx32a timing charateristics (continued) (worst-case commercial conditions v cca = 2.3 v, v cci = 4.75 v, t j = 70 c) (worst-case commercial conditions v cca = 3.0 v, v cci = 4.75 v, t j = 70 c) i/o module C ttl output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.5 2.9 3.3 3.9 ns t dhl data-to-pad high to low 3.1 3.6 4.1 4.8 ns t enzl enable-to-pad, z to l 2.6 3.0 3.4 4.0 ns t enzh enable-to-pad, z to h 2.3 2.7 3.0 3.6 ns t enlz enable-to-pad, l to z 3.4 3.9 4.4 5.2 ns t enhz enable-to-pad, h to z 4.2 4.8 5.5 6.313 ns i/o module C pci output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.8 3.2 3.7 4.3 ns t dhl data-to-pad high to low 3.4 3.9 4.5 5.3 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 ns t enzh enable-to-pad, z to h 1.5 1.7 1.9 2.2 ns t enlz enable-to-pad, l to z 2.6 3.0 3.5 4.1 ns t enhz enable-to-pad, h to z 3.3 3.9 4.4 5.2 ns
29 54sxa family fpgas a54sx32a timing characteristics (continued) (worst-case commercial conditions) dedicated (hard-wired) array clock network C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t hckh input low to high (pad to r-cell input) 1.3 1.4 1.6 1.9 ns t hckl input high to low (pad to r-cell input) 1.1 1.3 1.4 1.7 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.1 0.2 0.2 0.2 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.8 2.1 2.4 2.8 ns t rckl input high to low (light load) (pad to r-cell input) 2.0 2.3 2.6 3.0 ns t rckh input low to high (50% load) (pad to r-cell input) 2.0 2.4 2.7 3.1 ns t rckl input high to low (50% load) (pad to r-cell input) 2.2 2.5 2.8 3.3 ns t rckh input low to high (100% load) (pad to r-cell input) 2.6 3.0 3.4 4.0 ns t rckl input high to low (100% load) (pad to r-cell input) 2.6 3.0 3.4 4.0 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.9 1.0 1.1 1.3 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 ns t rcksw maximum skew (100% load) 1.3 1.5 1.7 2.0 ns
30 a54sx72a timing characteristics (worst-case commercial conditions, v cca, v cci = 3.0v, t j = 70 c) c-cell propagation delays 1 C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t pd internal array module 0.8 0.9 1.1 1.3 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.1 0.2 0.2 0.2 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 ns t rd2 fo=2 routing delay 0.4 0.5 0.6 0.7 ns t rd3 fo=3 routing delay 0.6 0.7 0.8 0.9 ns t rd4 fo=4 routing delay 0.7 0.9 1.0 1.1 ns t rd8 fo=8 routing delay 1.3 1.5 1.7 2.1 ns t rd12 fo=12 routing delay 1.9 2.2 2.5 3.0 ns r-cell timing t rco sequential clock-to-q 0.8 0.9 1.0 1.2 ns t clr asynchronous clear-to-q 0.6 0.7 0.8 0.9 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 ns t sud flip-flop data input set-up 0.4 0.5 0.6 0.7 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.0 1.2 1.4 1.6 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
31 a54sx72a timing characteristics (continued) (worst-case commercial conditions) i/o module input propagation delays C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t inyh input data pad-to-y high 0.6 0.7 0.8 0.9 ns t inyl input data pad-to-y low 0.9 1.0 1.2 1.4 ns predicted input routing delays 1 t ird1 fo=1 routing delay 0.3 0.3 0.4 0.5 ns t ird2 fo=2 routing delay 0.4 0.5 0.6 0.7 ns t ird3 fo=3 routing delay 0.6 0.7 0.8 0.9 ns t ird4 fo=4 routing delay 0.7 0.9 1.0 1.1 ns t ird8 fo=8 routing delay 1.3 1.5 1.7 2.1 ns t ird12 fo=12 routing delay 1.9 2.2 2.5 3.0 ns note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
54sxa family fpgas 32 a54sx72a timing charateristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) i/o module C pci output timing 1 C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.4 2.8 3.2 3.7 ns t dhl data-to-pad high to low 2.3 2.7 3.1 3.6 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 ns t enzh enable-to-pad, z to h 1.6 1.9 2.1 2.5 ns t enlz enable-to-pad, l to z 2.6 2.9 3.3 3.9 ns t enhz enable-to-pad, h to z 2.9 3.3 3.8 4.4 ns note: 1. delays based on 10pf loading. i/o module C ttl output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 3.2 3.7 4.2 4.9 ns t dhl data-to-pad high to low 2.8 3.3 3.7 4.4 ns t enzl enable-to-pad, z to l 2.6 3.0 3.4 4.0 ns t enzh enable-to-pad, z to h 3.2 3.7 4.2 4.9 ns t enlz enable-to-pad, l to z 2.1 3.2 3.6 4.2 ns t enhz enable-to-pad, h to z 3.3 3.8 4.3 5.0 ns
33 a54sx72a timing charateristics (continued) (worst-case commercial conditions v cca = 2.3 v, v cci = 4.75 v, t j = 70 c) (worst-case commercial conditions v cca = 3.0 v, v cci = 4.75 v, t j = 70 c) i/o module C ttl output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.5 2.9 3.3 3.9 ns t dhl data-to-pad high to low 3.1 3.6 4.1 4.8 ns t enzl enable-to-pad, z to l 2.6 3.0 3.4 4.0 ns t enzh enable-to-pad, z to h 2.3 2.7 3.0 3.6 ns t enlz enable-to-pad, l to z 3.4 3.9 4.4 5.2 ns t enhz enable-to-pad, h to z 4.2 4.8 5.5 6.3 ns i/o module C pci output timing C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t dlh data-to-pad low to high 2.8 3.2 3.7 4.3 ns t dhl data-to-pad high to low 3.4 3.9 4.5 5.3 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 ns t enzh enable-to-pad, z to h 1.5 1.7 1.9 2.2 ns t enlz enable-to-pad, l to z 2.6 3.0 3.5 4.1 ns t enhz enable-to-pad, h to z 3.3 3.9 4.4 5.2 ns
54sxa family fpgas 34 a54sx72a timing characteristics (continued) (worst-case commercial conditions) dedicated (hard-wired) array clock network C3 speed C2 speed C1 speed std speed parameter description min. max. min. max. min. max. min. max. units t hckh input low to high (pad to r-cell input) 1.6 1.9 2.1 2.5 ns t hckl input high to low (pad to r-cell input) 1.4 1.6 1.8 2.2 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.3 0.4 0.4 0.5 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 2.8 3.2 3.6 4.2 ns t rckl input high to low (light load) (pad to r-cell input) 2.9 3.4 3.8 4.5 ns t rckh input low to high (50% load) (pad to r-cell input) 3.4 3.9 4.4 5.2 ns t rckl input high to low (50% load) (pad to r-cell input) 3.5 4.0 4.5 5.3 ns t rckh input low to high (100% load) (pad to r-cell input) 4.6 5.3 6.0 7.0 ns t rckl input high to low (100% load) (pad to r-cell input) 4.6 5.3 6.0 7.1 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.9 1.0 1.1 1.3 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 ns t rcksw maximum skew (100% load) 1.3 1.5 1.7 2.0 ns
35 package pin assignments 208-pin pqfp (top view) 208-pin pqfp 1 208
54sxa family fpgas 36 208-pin pqfp pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function 1 gnd gnd gnd 54 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 55 i/o i/o i/o 3 i/o i/o i/o 56 i/o i/o i/o 4 nc i/o i/o 57 i/o i/o i/o 5 i/o i/o i/o 58 i/o i/o i/o 6 nc i/o i/o 59 i/o i/o i/o 7 i/o i/o i/o 60 v cci v cci v cci 8 i/o i/o i/o 61 nc i/o i/o 9 i/o i/o i/o 62 i/o i/o i/o 10 i/o i/o i/o 63 i/o i/o i/o 11 tms tms tms 64 nc i/o i/o 12 v cci v cci v cci 65* i/o i/o nc* 13 i/o i/o i/o 66 i/o i/o i/o 14 nc i/o i/o 67 nc i/o i/o 15 i/o i/o i/o 68 i/o i/o i/o 16 i/o i/o i/o 69 i/o i/o i/o 17 nc i/o i/o 70 nc i/o i/o 18 i/o i/o i/o 71 i/o i/o i/o 19 i/o i/o i/o 72 i/o i/o i/o 20 nc i/o i/o 73 nc i/o i/o 21 i/o i/o i/o 74 i/o i/o i/o 22 i/o i/o i/o 75 nc i/o i/o 23 nc i/o i/o 76 prb, i/o prb, i/o prb, i/o 24 i/o i/o i/o 77 gnd gnd gnd 25 nc nc nc 78 v cca v cca v cca 26 gnd gnd gnd 79 gnd gnd gnd 27 v cca v cca v cca 80 nc nc nc 28 gnd gnd gnd 81 i/o i/o i/o 29 i/o i/o i/o 82 hclk hclk hclk 30 i/o i/o i/o 83 i/o i/o i/o 31 nc i/o i/o 84 i/o i/o i/o 32 i/o i/o i/o 85 nc i/o i/o 33 i/o i/o i/o 86 i/o i/o i/o 34 i/o i/o i/o 87 i/o i/o i/o 35 nc i/o i/o 88 nc i/o i/o 36 i/o i/o i/o 89 i/o i/o i/o 37 i/o i/o i/o 90 i/o i/o i/o 38 i/o i/o i/o 91 nc i/o i/o 39 nc i/o i/o 92 i/o i/o i/o 40 v cci v cci v cci 93 i/o i/o i/o 41 v cca v cca v cca 94 nc i/o i/o 42 i/o i/o i/o 95 i/o i/o i/o 43 i/o i/o i/o 96 i/o i/o i/o 44 i/o i/o i/o 97 nc i/o i/o 45 i/o i/o i/o 98 v cci v cci v cci 46 i/o i/o i/o 99 i/o i/o i/o 47 i/o i/o i/o 100 i/o i/o i/o 48 nc i/o i/o 101 i/o i/o i/o 49 i/o i/o i/o 102 i/o i/o i/o 50 nc i/o i/o 103 tdo, i/o tdo, i/o tdo, i/o 51 i/o i/o i/o 104 i/o i/o i/o 52 gnd gnd gnd 105 gnd gnd gnd 53 i/o i/o i/o 106 nc i/o i/o 107 i/o i/o i/o 158 i/o i/o i/o * please note that pin 65 in the a54sx32apq208 is a no connect (nc).
37 108 nc i/o i/o 159 i/o i/o i/o 109 i/o i/o i/o 160 i/o i/o i/o 110 i/o i/o i/o 161 i/o i/o i/o 111 i/o i/o i/o 162 i/o i/o i/o 112 i/o i/o i/o 163 i/o i/o i/o 113 i/o i/o i/o 164 v cci v cci v cci 114 v cca v cca v cca 165 i/o i/o i/o 115 v cci v cci v cci 166 i/o i/o i/o 116 nc i/o i/o 167 nc i/o i/o 117 i/o i/o i/o 168 i/o i/o i/o 118 i/o i/o i/o 169 i/o i/o i/o 119 nc i/o i/o 170 nc i/o i/o 120 i/o i/o i/o 171 i/o i/o i/o 121 i/o i/o i/o 172 i/o i/o i/o 122 nc i/o i/o 173 nc i/o i/o 123 i/o i/o i/o 174 i/o i/o i/o 124 i/o i/o i/o 175 i/o i/o i/o 125 nc i/o i/o 176 nc i/o i/o 126 i/o i/o i/o 177 i/o i/o i/o 127 i/o i/o i/o 178 i/o i/o i/o 128 i/o i/o i/o 179 i/o i/o i/o 129 gnd gnd gnd 180 clka clka clka 130 v cca v cca v cca 181 clkb clkb clkb 131 gnd gnd gnd 182 nc nc nc 132 nc nc nc 183 gnd gnd gnd 133 i/o i/o i/o 184 v cca v cca v cca 134 i/o i/o i/o 185 gnd gnd gnd 135 nc i/o i/o 186 pra, i/o pra, i/o pra, i/o 136 i/o i/o i/o 187 i/o i/o i/o 137 i/o i/o i/o 188 i/o i/o i/o 138 nc i/o i/o 189 nc i/o i/o 139 i/o i/o i/o 190 i/o i/o i/o 140 i/o i/o i/o 191 i/o i/o i/o 141 nc i/o i/o 192 nc i/o i/o 142 i/o i/o i/o 193 i/o i/o i/o 143 nc i/o i/o 194 i/o i/o i/o 144 i/o i/o i/o 195 nc i/o i/o 145 v cca v cca v cca 196 i/o i/o i/o 146 gnd gnd gnd 197 i/o i/o i/o 147 i/o i/o i/o 198 nc i/o i/o 148 v cci v cci v cci 199 i/o i/o i/o 149 i/o i/o i/o 200 i/o i/o i/o 150 i/o i/o i/o 201 v cci v cci v cci 151 i/o i/o i/o 202 nc i/o i/o 152 i/o i/o i/o 203 nc i/o i/o 153 i/o i/o i/o 204 i/o i/o i/o 154 i/o i/o i/o 205 nc i/o i/o 155 nc i/o i/o 206 i/o i/o i/o 156 nc i/o i/o 207 i/o i/o i/o 157 gnd gnd gnd 208 tck, i/o tck, i/o tck, i/o 208-pin pqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function * please note that pin 65 in the a54sx32apq208 is a no connect (nc).
38 package pin assignments (continued) 100-pin tqfp (top view) 1 100-pin vqfp 100
39 54sxa family fpgas 100-tqfp pin number a54sx08a function a54sx16a function pin number a54sx08a function a54sx16a function 1 gnd gnd 51 gnd gnd 2 tdi, i/o tdi, i/o 52 i/o i/o 3 i/o i/o 53 i/o i/o 4 i/o i/o 54 i/o i/o 5 i/o i/o 55 i/o i/o 6 i/o i/o 56 i/o i/o 7 tms tms 57 v cca v cca 8v cci v cci 58 v cci v cci 9 gnd gnd 59 i/o i/o 10 i/o i/o 60 i/o i/o 11 i/o i/o 61 i/o i/o 12 i/o i/o 62 i/o i/o 13 i/o i/o 63 i/o i/o 14 i/o i/o 64 i/o i/o 15 i/o i/o 65 i/o i/o 16 i/o i/o 66 i/o i/o 17 i/o i/o 67 v cca v cca 18 i/o i/o 68 gnd gnd 19 i/o i/o 69 gnd gnd 20 v cci v cci 70 i/o i/o 21 i/o i/o 71 i/o i/o 22 i/o i/o 72 i/o i/o 23 i/o i/o 73 i/o i/o 24 i/o i/o 74 i/o i/o 25 i/o i/o 75 i/o i/o 26 i/o i/o 76 i/o i/o 27 i/o i/o 77 i/o i/o 28 i/o i/o 78 i/o i/o 29 i/o i/o 79 i/o i/o 30 i/o i/o 80 i/o i/o 31 i/o i/o 81 i/o i/o 32 i/o i/o 82 v cci v cci 33 i/o i/o 83 i/o i/o 34 prb, i/o prb, i/o 84 i/o i/o 35 v cca v cca 85 i/o i/o 36 gnd gnd 86 i/o i/o 37 nc nc 87 clka clka 38 i/o i/o 88 clkb clkb 39 hclk hclk 89 nc nc 40 i/o i/o 90 v cca v cca 41 i/o i/o 91 gnd gnd 42 i/o i/o 92 pra, i/o pra, i/o 43 i/o i/o 93 i/o i/o 44 v cci v cci 94 i/o i/o 45 i/o i/o 95 i/o i/o 46 i/o i/o 96 i/o i/o 47 i/o i/o 97 i/o i/o 48 i/o i/o 98 i/o i/o 49 tdo, i/o tdo, i/o 99 i/o i/o 50 i/o i/o 100 tck, i/o tck, i/o
40 package pin assignments (continued) 144-pin tqfp (top view) 1 144 144-pin tqfp
41 54sxa family fpgas 144-pin tqfp pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function 1 gnd gnd gnd 41 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 42 i/o i/o i/o 3 i/o i/o i/o 43 i/o i/o i/o 4 i/o i/o i/o 44 v cci v cci v cci 5 i/o i/o i/o 45 i/o i/o i/o 6 i/o i/o i/o 46 i/o i/o i/o 7 i/o i/o i/o 47 i/o i/o i/o 8 i/o i/o i/o 48 i/o i/o i/o 9 tms tms tms 49 i/o i/o i/o 10 v cci v cci v cci 50 i/o i/o i/o 11 gnd gnd gnd 51 i/o i/o i/o 12 i/o i/o i/o 52 i/o i/o i/o 13 i/o i/o i/o 53 i/o i/o i/o 14 i/o i/o i/o 54 prb, i/o prb, i/o prb, i/o 15 i/o i/o i/o 55 i/o i/o i/o 16 i/o i/o i/o 56 v cca v cca v cca 17 i/o i/o i/o 57 gnd gnd gnd 18 i/o i/o i/o 58 nc nc nc 19 nc nc nc 59 i/o i/o i/o 20 v cca v cca v cca 60 hclk hclk hclk 21 i/o i/o i/o 61 i/o i/o i/o 22 i/o i/o i/o 62 i/o i/o i/o 23 i/o i/o i/o 63 i/o i/o i/o 24 i/o i/o i/o 64 i/o i/o i/o 25 i/o i/o i/o 65 i/o i/o i/o 26 i/o i/o i/o 66 i/o i/o i/o 27 i/o i/o i/o 67 i/o i/o i/o 28 gnd gnd gnd 68 v cci v cci v cci 29 v cci v cci v cci 69 i/o i/o i/o 30 v cca v cca v cca 70 i/o i/o i/o 31 i/o i/o i/o 71 tdo, i/o tdo, i/o tdo, i/o 32 i/o i/o i/o 72 i/o i/o i/o 33 i/o i/o i/o 73 gnd gnd gnd 34 i/o i/o i/o 74 i/o i/o i/o 35 i/o i/o i/o 75 i/o i/o i/o 36 gnd gnd gnd 76 i/o i/o i/o 37 i/o i/o i/o 77 i/o i/o i/o 38 i/o i/o i/o 78 i/o i/o i/o 39 i/o i/o i/o 79 v cca v cca v cca 40 i/o i/o i/o 80 v cci v cci v cci
42 81 gnd gnd gnd 113 i/o i/o i/o 82 i/o i/o i/o 114 i/o i/o i/o 83 i/o i/o i/o 115 v cci v cci v cci 84 i/o i/o i/o 116 i/o i/o i/o 85 i/o i/o i/o 117 i/o i/o i/o 86 i/o i/o i/o 118 i/o i/o i/o 87 i/o i/o i/o 119 i/o i/o i/o 88 i/o i/o i/o 120 i/o i/o i/o 89 v cca v cca v cca 121 i/o i/o i/o 90 nc nc nc 122 i/o i/o i/o 91 i/o i/o i/o 123 i/o i/o i/o 92 i/o i/o i/o 124 i/o i/o i/o 93 i/o i/o i/o 125 clka clka clka 94 i/o i/o i/o 126 clkb clkb clkb 95 i/o i/o i/o 127 nc nc nc 96 i/o i/o i/o 128 gnd gnd gnd 97 i/o i/o i/o 129 v cca v cca v cca 98 v cca v cca v cca 130 i/o i/o i/o 99 gnd gnd gnd 131 pra, i/o pra, i/o pra, i/o 100 i/o i/o i/o 132 i/o i/o i/o 101 gnd gnd gnd 133 i/o i/o i/o 102 v cci v cci v cci 134 i/o i/o i/o 103 i/o i/o i/o 135 i/o i/o i/o 104 i/o i/o i/o 136 i/o i/o i/o 105 i/o i/o i/o 137 i/o i/o i/o 106 i/o i/o i/o 138 i/o i/o i/o 107 i/o i/o i/o 139 i/o i/o i/o 108 i/o i/o i/o 140 v cci v cci v cci 109 gnd gnd gnd 141 i/o i/o i/o 110 i/o i/o i/o 142 i/o i/o i/o 111 i/o i/o i/o 143 i/o i/o i/o 112 i/o i/o i/o 144 tck, i/o tck, i/o tck, i/o 113 i/o i/o i/o 144-pin tqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function
43 54sxa family fpgas package pin assignments (continued) 329-pin bga (top view) 23 22 21 20 19 18 17 16 15 14 10 11 12 13 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac
44 329-pin bga pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function a1 gnd aa9 i/o ac8 i/o c7 i/o a10 i/o ab1 i/o ac9 v cci c8 i/o a11 i/o ab10 i/o b1 v cci c9 i/o a12 i/o ab11 prb, i/o b10 i/o d1 i/o a13 clkb ab12 i/o b11 i/o d10 i/o a14 i/o ab13 hclk b12 pra, i/o d11 v cca a15 i/o ab14 i/o b13 clka d12 nc a16 i/o ab15 i/o b14 i/o d13 i/o a17 i/o ab16 i/o b15 i/o d14 i/o a18 i/o ab17 i/o b16 i/o d15 i/o a19 i/o ab18 i/o b17 i/o d16 i/o a2 gnd ab19 i/o b18 i/o d17 i/o a20 i/o ab2 gnd b19 i/o d18 i/o a21 nc ab20 i/o b2 gnd d19 i/o a22 v cci ab21 i/o b20 i/o d2 i/o a23 gnd ab22 gnd b21 i/o d20 i/o a3 v cci ab23 i/o b22 gnd d21 i/o a4 nc ab3 i/o b23 v cci d22 i/o a5 i/o ab4 i/o b3 i/o d23 i/o a6 i/o ab5 i/o b4 i/o d3 i/o a7 v cci ab6 i/o b5 i/o d4 tck, i/o a8 nc ab7 i/o b6 i/o d5 i/o a9 i/o ab8 i/o b7 i/o d6 i/o aa1 v cci ab9 i/o b8 i/o d7 i/o aa10 i/o ac1 gnd b9 i/o d8 i/o aa11 i/o ac10 i/o c1 nc d9 i/o aa12 i/o ac11 i/o c10 i/o e1 v cci aa13 i/o ac12 i/o c11 i/o e2 i/o aa14 i/o ac13 i/o c12 i/o e20 i/o aa15 i/o ac14 i/o c13 i/o e21 i/o aa16 i/o ac15 nc c14 i/o e22 i/o aa17 i/o ac16 i/o c15 i/o e23 i/o aa18 i/o ac17 i/o c16 i/o e3 i/o aa19 i/o ac18 i/o c17 i/o e4 i/o aa2 i/o ac19 i/o c18 i/o f1 i/o aa20 tdo, i/o ac2 v cci c19 i/o f2 tms aa21 v cci ac20 i/o c2 tdi, i/o f20 i/o aa22 i/o ac21 nc c20 i/o f21 i/o aa23 v cci ac22 v cci c21 v cci f22 i/o aa3 gnd ac23 gnd c22 gnd f23 i/o aa4 i/o ac3 nc c23 nc f3 i/o aa5 i/o ac4 i/o c3 gnd f4 i/o aa6 i/o ac5 i/o c4 i/o g1 i/o aa7 i/o ac6 i/o c5 i/o g2 i/o aa8 i/o ac7 i/o c6 i/o g20 i/o
45 54sxa family fpgas g21 i/o l3 i/o r22 i/o y18 i/o g22 i/o l4 nc r23 i/o y19 i/o g23 gnd m1 i/o r3 i/o y2 i/o g3 i/o m10 gnd r4 i/o y20 gnd g4 i/o m11 gnd t1 i/o y21 i/o h1 i/o m12 gnd t2 i/o y22 i/o h2 i/o m13 gnd t20 i/o y23 i/o h20 v cca m14 gnd t21 i/o y3 i/o h21 i/o m2 i/o t22 i/o y4 gnd h22 i/o m20 v cca t23 i/o y5 i/o h23 i/o m21 i/o t3 i/o y6 i/o h3 i/o m22 i/o t4 i/o y7 i/o h4 i/o m23 v cci u1 i/o y8 i/o j1 nc m3 i/o u2 i/o y9 i/o j2 i/o m4 v cca u20 i/o j20 i/o n1 i/o u21 v cca j21 i/o n10 gnd u22 i/o j22 i/o n11 gnd u23 i/o j23 i/o n12 gnd u3 v cca j3 i/o n13 gnd u4 i/o j4 i/o n14 gnd v1 v cci k1 i/o n2 i/o v2 i/o k10 gnd n20 nc v20 i/o k11 gnd n21 i/o v21 i/o k12 gnd n22 i/o v22 i/o k13 gnd n23 i/o v23 i/o k14 gnd n3 i/o v3 i/o k2 i/o n4 i/o v4 i/o k20 i/o p1 i/o w1 i/o k21 i/o p10 gnd w2 i/o k22 i/o p11 gnd w20 i/o k23 i/o p12 gnd w21 i/o k3 i/o p13 gnd w22 i/o k4 i/o p14 gnd w23 nc l1 i/o p2 i/o w3 i/o l10 gnd p20 i/o w4 i/o l11 gnd p21 i/o y1 nc l12 gnd p22 i/o y10 i/o l13 gnd p23 i/o y11 i/o l14 gnd p3 i/o y12 v cca l2 i/o p4 i/o y13 nc l20 nc r1 i/o y14 i/o l21 i/o r2 i/o y15 i/o l22 i/o r20 i/o y16 i/o l23 nc r21 i/o y17 i/o 329-pin bga pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function

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